It is often desirable to impose a field-effect transistor (FET) buffer amplifier in a signal path because such an amplifier exhibits a high input impedance to minimize loading a previous stage, and yet provides a low output impedance. Other requirements for such a buffer amplifier may include high linearity and low thermal distortion to maintain signal accuracy and fidelity, as well as high bandwidth capability. A buffer amplifier addressing these problems is the subject matter of U.S. Pat. No. 4,390,852 granted to John L. Addis, and assigned to the assignee of the present invention.
A problem not addressed by the foregoing prior art buffer amplifier, however, is the fact that FETs are susceptible to power supply noise because of channel length modulation effects of drain voltage, as well as other noise effects. In operating environments such as sweep-ramp generating circuits of oscilloscopes where the input gate of the buffer amplifier is connected directly to a sweep timing capacitor, very low noise and good linearity are essential.